Integrated Circuit. Transistor Transistor Logic (TTL). 4−Line−to−16−Line Decoder /Demultiplexer. 24−Lead DIP Type Package. Description: The NTE is a. 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test . datasheet, circuit, data sheet: NSC – 4-Line to Line for Electronic Components and Semiconductors, integrated circuits, diodes, triacs.

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High speed signals were usually active low, for datasheey the same reason. Email Required, but never shown. WhatRoughBeast 49k 2 28 Home Questions Tags Users Unanswered. The actual implementation of the chosen ic has active low outputs.

Sign up using Facebook. So TTL circuitry adopted asymmetric logic levels, where ‘0’ was guaranteed to be below 0. If you have some experience using BJTs you will know that NPN transistors are best used to pull a signal to 0V common emitter, with the output connected to 7415 collector and quite weak at pulling a signal high. The active-low output is just how the design for that specific decoder was carried out – there is also active-high varieties.

National Semiconductor

There are probably two enable inputs because otherwise there would be two unused pins on the 24 pin package 741554 don’t recall seeing 22 pin DIP packages. Each of the 16 outputs can be connected through a resistor and then through an LED to serve as a simple 16 LED controller.


All the other ouputs stay high. Rather than providing only a single enable, both pins are used.

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This carried through to the input current requirements: Email Required, but never shown. It is counterintuitive yes, but it is a well-established dagasheet that the sort of devices that this part will be controlling will have active-low enable inputs. Sign up using Email and Password. Sign up using Email and Password. Each or these 4-line-toline decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen mutually exclusive outputs when both the strobe inputs, G1 and G2, are low.

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According to the internal logic diagram on the datasheet, the G inputs are connected to a two-input AND gate with inverting inputs, whose output feeds one input of all the NAND gates that produce the outputs. Post Your Answer Discard By clicking “Post Your Answer”, you acknowledge that you have read our updated terms of serviceprivacy policy and cookie policyand that your continued use of the website is oc to these policies.


Sign up or log in Sign up using Google. This is the image of a 1 to 16 demux. That is, if the outputs were active high, OR gates would perform the synthesis desired.

National Semiconductor – datasheet pdf

As for the NAND gates, there is a function being implemented in which the iv are there to realize it. So they are inverted a explained in the theory.

These demultiplexers are ideally suited for implementing high-performance memory decoders. Sign up or log in Sign up using Google. My first question is more important I understand how it works.

(PDF) 74154 Datasheet download

And that’s what is going on with the By using our site, you acknowledge that you have read and understand our Cookie PolicyPrivacy Policyand our Terms of Service. And why are there 2 of them, you ask? Will someone please explain the purpose of inverting the outputs 0 through 15 as well as the use the NAND gates here?

So is it possible that both enables are hooked to a 2-input OR gate; this is just making use of the extra pins to make 24? Understand, this is a typical example of application, not it’s sole purpose. All inputs are buffered and input clamping diodes are provided to minimize transmission-line effects and thereby simplify system design.