Then a new device which is named Inter-line Dynamic Voltage Restorer (IDVR) is discussed. This device consists of two conventional DVRs which are installed. An interline dynamic voltage restorer (IDVR) is a novel c o m p e n s a t i o n piece of mitigation It is made of several dynamic voltage restorers (DVRs) with a. Index Terms—Dynamic voltage restorer, Interline dynamic voltage restorer, Current source inverter, SMES and Power quality.

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In this paper, a new configuration has been proposed which not only improves the compensation capacity of the IDVR at high power factors, but also increases the performance of the compensator to mitigate deep sags at fairly moderate power factors. These advantages were achieved by decreasing the load power factor during sag condition.

The compensation was eventually forced to stop before the entire voltage sag period was restorrer.

The proposed concept has been supported with simulation and experimental results. These operational constraints have been identified and considered. The higher active power requirement associated with voltage phase jump compensation has caused a substantial rise in size and cost of dc link energy storage system of DVR. The DF of the sourcing feeder increases while the DF of the receiving feeder decreases.

Strathprints home Open Access Login. The overall three-phase voltage signals during in-phase compensation simulation. The proposed strategy improves the voltage quality of sensitive loads by protecting them against the grid voltage sags involving the phase jump. Electronics Nuclear engineering, Electrical and Electronic Engineering. In this technique, the source voltages are sensed continuously and when the voltage sag is detected, the shunt reactances are switched into the circuit and decrease the load power factors to improve IDVR performance.

The experimental test results match those proposed using simulation, although some discrepancies due to the imperfect nature of the test circuit components were seen. Finally, the simulation and practical results on the CHB based IDVR confirmed the effectiveness of the proposed configuration and control scheme. An interline dynamic voltage restorer IDVR is a new device for sag mitigation which is made of several dynamic voltage restorers DVRs with dynamiic common DC link, where each DVR is connected in series with a distribution dynwmic.


During sag period, active power can be transferred from a feeder to another one and voltage sags with long durations can be mitigated.

This enhancement can also be seen as a considerable reduction in dc link capacitor size for new installation. This study aims to enhance the abilities of DVRs to maintain acceptable voltages and last longer during compensation. To successfully apply this concept, several constraints are addressed throughout the paper. This paper presents a utilization technique for enhancing the capabilities of dynamic voltage restorers DVRs. It also increases compensation time by operating in minimum active power mode through a controlled transition once the phase jump is volage.

Winter Meetingvol. Per-phase simulation results for voltage sag condition at: Mathematical analysis is carried reestorer for each individual component of the IDVR as modular models, which are then aggregated to generate the final model. This paper proposes a new operational mode for the IDVR to improve the Imterline of different feeders under normal operation.

IDVR compensation capacity, however, depends greatly on the load power factor and a higher load power factor causes lower performance of IDVR. The existing control strategies either mitigate the phase jump or improve the utilization of dc link energy by i reducing the amplitude of injected voltage, or ii optimizing the dc bus energy support. Instead of bypassing the DVRs in normal conditions, this paper proposes operating the DVRs, if needed, to improve the displacement factor DF of one of the involved feeders.

The performance of proposed method is evaluated using simulation study. To illustrate the effectiveness of the proposed method an analytical comparison is carried out with the existing phase jump compensation schemes.

Per-phase experimental and corresponding simulation results for DF improvement case: DF improvement can be achieved via active and reactive power exchange PQ sharing between different feeders. In this case, the DF of the sourcing feeder will have a notable improvement with only a slight variation in DF of the receiving feeder.

The proposed technique has the advantage of simplifying the modelling of any flexible AC transmission system FACTS device in dynamic phasor mode when compared to other modelling techniques reported in the literature.


Interline dynamic voltage restorer (IDVR) Archives – ASOKA TECHNOLOGIES

With this technique, none or less of the real power will be transferred to the system, which provides more for the DVR to cover a wider range of voltage sags, adding more flexible adaptive control to the solution of sag voltage disturbances. The overall three-phase voltage signals during zero-real power dynaic compensation dynwmic. A method for building a dynamic phasor model of an Interline Dynamic Voltage Restorer IDVR is presented, and the resulting model is tested in a simple radial distribution system.

Then, experimental results on a scaled-down IDVR are presented to confirm the theoretical and simulation results. For normal voltage levels, the DVRs should be bypassed.

This technical merit demonstrates that DVRs could cover a wider range of voltage sags; the practicality of this idea for better utilization is better than that of existing installed DVRs. Then, more of the energy stored in the DC-link capacitor was utilized quickly, reaching its limitation within a shorter period.

The main conclusions of this work can be summarized as follows:. This paper deals with improving the voltage quality of sensitive loads from voltage sags using dynamic voltage restorer DVR. In this paper an enhanced sag compensation scheme is proposed for capacitor supported DVR.

In this paper, an enhanced sag compensation strategy is proposed that mitigates the phase jump in the load voltage while improving the dynamicc sag compensation time.

Transient analysis of interline dynamic voltage restorer using dynamic phasor representation

Simulation and experimental results elucidate and intwrline the proposed concept. To overcome this limitation, a new idea is presented in this paper which allows to reduce the load power factor under sag condition, and therefore, the compensation capacity is increased. With the traditional in-phase technique, the compensation was performed and depended on the real power injected to the system.

Both the magnitude and phase displacement angle of the synthesized DVR voltage are precisely adjusted to achieve lower power utilization.